RXRTSE=0, TXRTSPOL=0, TXCTSE=0, TXRTSE=0
UART Modem Register
| TXCTSE | Transmitter clear-to-send enable 0 (0): CTS has no effect on the transmitter. 1 (1): Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission. |
| TXRTSE | Transmitter request-to-send enable 0 (0): The transmitter has no effect on RTS. 1 (1): When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. (FIFO) (FIFO) |
| TXRTSPOL | Transmitter request-to-send polarity 0 (0): Transmitter RTS is active low. 1 (1): Transmitter RTS is active high. |
| RXRTSE | Receiver request-to-send enable 0 (0): The receiver has no effect on RTS. 1 (1): RTS is deasserted if the number of characters in the receiver data register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted when the number of characters in the receiver data register (FIFO) is less than RWFIFO[RXWATER]. |